On-chip debugging (OCD) is a
method to start, stop and read the core of a Microcontroller
(MCU) or an application by having additional silicon on every
MCU of a distinct manufacturer’s series. To access this specific
MCU area one or more dedicated pins are used. Those are then no
longer available to the developer and/or designer. These pins
are referenced as the OCD interface. Often these lines can be
used in multiple ways. This must be considered when designing
the target hardware.
ARM-Cortex uses JTAG as OCD interface. This interface was
originally designed for boundary scan testing and uses at least
5 pins (plus ground).
Download the complete article about debug interfaces of
ARM-Cortex
For challenging real-time applications (e.g. in
avionic, automotive and medical systems) the basic JTAG debug
functions are not sufficient. There is no way to evaluate the
real-time behaviour without elaborate and time-consuming code
instrumentation, DCC usage, code analysis tools and/or expensive
simulators that change the run-time behaviour of the
application. Due to that development times for applications
increase while the test opportunities decrease. |
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To improve this, ARM-Cortex offers an add-on that can be
licensed and included in the MCU by the MCU manufacturer: ETM =
Embedded Trace Macrocell.
ETM is an add-on on ARM CORE with different characteristics that
allows recording the program flow and with some restrictions
data accesses. ETM is a superset of JTAG debugging and needs
more dedicated pins and chip space as pure JTAG.
ARM-CORTEX CoreSight technology includes many new features:
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Less pins are necessary because the hardware debugger can be
connected by JTAG or by 2 pins only – “Serial Wire Debug” = SWD
(+GND + RESET + pot. VREF). This is a major advantage on low-pin
count MCUs.
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SWD provides real-time watches that allow regular view and
update of variable content in real-time.
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To access the internal asynchronous trace functions SWDIO
(=TMS) and SWDCLK (=TCLK) and an additional pin SWO (=TDO) are
used. This asynchronous trace is called Serial Wire Trace (SWT).
With that every 64 CPU cycles the program counter can be dumped
for a snapshot of the program flow.
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SWT allows to trigger on data access and to dump these values
and/or program counter. In case of asynchronous trace this
output is restricted by the bottle neck of the serial line that
leads often to “trace hardware overflows”. Therefore trace data
volume should be limited and tests should be limited to small
parts of the application.
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Another nice feature is the Instrumentation Trace Modul (ITM).
Like a “printf” values can be written to specific virtual trace
ports with a few commands in the application. These ports can be
read by SWT.
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